An information processing apparatus includes a plurality of control circuits performing a predetermined process. An interruption controller as one of the control circuits is arranged between a peripheral device and a central processing unit (CPU), and connected to the peripheral device and the CPU. One example of the CPU is a digital signal processor (DSP) executing a variety of processes.
The interruption controller receives from an external device an interrupting signal serving as a trigger signal triggering the predetermined process, and sends the interrupting signal to the DSP while determining the priority of the process and the timing of the process. Upon receiving the interrupting signal from the interruption controller, the DSP executes a process desired by the external device as a sending source of the interrupting signal. The interruption controller and the DSP are set to be operational in response to a clock signal.
Referring to FIGS. 7-9, the interruption controller and the DSP are discussed in detail below. FIGS. 7-9 illustrate a terminal device, such as a cellular phone, including the interruption controller and the DSP. As illustrated in FIGS. 7-9, the terminal device is a multi-DSP in which the two DSPs are related with one serving as a master and the other serving as a slave.
Referring to FIG. 7, a structure of the terminal device of related art is described. FIG. 7 illustrates the structure of the terminal device of related art. For example, the terminal device of FIG. 7 includes an antenna, a radio-frequency module, a baseband module, an interface module interfacing with the outside, a memory, application, and a power source. The baseband module includes a searcher, a demodulator, a decoder, an encoder, a modulator, and a command controller. The interface module interfacing with the outside includes a loudspeaker, a liquid-crystal display (LCD), a universal serial bus (USB), a camera, keys (control keys), and a microphone.
The antenna exchanges a variety of signals with a base station (not illustrated) and another terminal device. The radio-frequency module performs a control process related to transmission and reception of the variety of signals via the antenna. The command controller performs a variety of control processes in accordance with an application and a program stored in the memory. The demodulator demodulates an input signal. The modulator modulates a signal in accordance with a predetermined modulation method. The decoder decodes the input signal. The encoder generates encoded data. The searcher is described later.
The loudspeaker emits sounds. The microphone picks up sounds coming in through a prescribed opening. The LCD is a display. The keys are an input device inputting a variety of information and operation commands. The USB is a data transfer path connecting the terminal device to a peripheral device. The camera captures a still image or a moving image, and generates image data. The memory stores data related to a variety of processes and a variety of results of the processes. The application is a predetermined program. The power source supplies power to the terminal device.
Referring to FIG. 8, a structure of the searcher of related art is described below. FIG. 8 illustrates the structure of the searcher of related art. As illustrated in FIG. 8, interruption factors and interrupting signals are denoted by broken lines, internal bus signals are denoted by solid lines, and main input-output signals are denoted by heavy solid lines. The interruption factors are identical to the interrupting signals. The interruption controller performs a mask process on an interrupting signal. In the input phase of the interrupting signal to the interruption controller, the interrupting signal is referred to as an interruption factor.
Referring to FIG. 8, the searcher includes a command receiver, a command responding unit, a cell search unit, a path search processor, a fast Fourier transform (FFT) unit, and a bus controller. The searcher further includes an interruption controller (master), a DSP (master), an interruption controller (slave), and a DSP (slave).
The command receiver receives a command from the command controller and the command responding unit responds to a command from the command controller. Upon receiving a command, the searcher starts a cell search process, a path search process, and an FFT process. Upon completing each of the processes, the searcher performs a response process to the command.
The cell search processor includes a primary search channel (PSCH) processor, and a secondary search channel (SSCH) processor. The cell search processor detects a cell from a received signal, and detects a timing of a leading part of a radio-frequency frame. The path search processor detects from the received signal a timing of a leading part of an updated radio-frequency frame in response to the timing of the leading part of the radio-frequency frame detected by the cell search processor. The path search processor then determines a symbol timing from the detected timing of the leading part of the radio-frequency frame. The FFT processor performs a fast Fourier transform at the symbol timing determined by the path search processor.
The interruption controller (master) and the interruption controller (slave) receive the interrupting signals from each of the command receiver, the command responding unit, the cell search processor, the path search processor and the FFT processor. The interruption controller (master) and the interruption controller (slave) sends the received interrupting signals to the DSP (master) and the DSP (slave), respectively.
The DSP (master) manages command reception, command response, and startup processes. The DSP (slave) performs a cell search process and a path search process together with the cell search processor, and the path search processor, respectively. The bus controller inputs a bus signal received from each of the above-described elements to the command receiver and the command responding unit.
Referring to FIG. 9, the interrupting signal and the clock signal in the multi-DSP of related art are described. FIG. 9 illustrates the interrupting signal and the clock signal in the multi-DSP of related art. As illustrated in FIG. 9, a common clock signal (labeled CLK as illustrated) is supplied to the DSP (master), the DSP (slave), the interruption controller (master), and the interruption controller (slave). Upon receiving the clock signal, these elements are set to be operational.
With the clock signal supplied, the interruption controller (master) receives interruption factors A-C and an inter-DSP (slave) between the interruption controllers, and outputs the interrupting signal to the DSP (master). The inter-DSP interruption is sent after the completion of the process in the DSP, and is an interrupting signal to be exchanged between the master and the slave.
Similarly, with the clock signal supplied, the interruption controller (slave) receives interruption factors A-C and an inter-DSP (master) between the interruption controllers, and outputs the interrupting signal to the DSP (slave). The interruption controller (master) and the interruption controller (slave) are identical in circuit arrangement, and different only in the connection of terminals thereof to the outside.
The DSP (master) receives the interrupting signal from the interruption controller (master) and executes a desired process. The DSP (master), in response to a process completion notification, executes an inter-DSP interruption, masks the interruption factor or the interrupting signal in the interruption controller (master), and registers access to the interruption controller (master) to acquire the interruption factor.
The DSP (slave) executes a desired process in response to the reception of the interrupting signal from the interruption controller (slave). The DSP (slave) also executes an inter-DSP interruption responsive to a process completion notification, masks the interruption factor or the interrupting signal in the interruption controller (slave), and registers access to the interruption controller (slave) to acquire the interruption factor. Japanese Laid-open Patent Publication No. 7-261869 and Japanese Laid-open Patent Publication No. 7-121195 describe a related art technique in which the supply of a clock signal to a DSP is stopped when the DSP has not completed the relevant processing.
The related art technique has a problem that extra power is consumed. For example, an operational status is set in response to the supply of a clock signal, and out of the related interruption controller and DSP, the interruption controller is continuously supplied with the clock signal. In the related art technique, an interruption controller not executing any process consumes extra power, such as power consumed during an idling period. As a result, the DSP and the interruption controller not executing any process remain in an operational status, and extra power is consumed.